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Obsolete Device
Please use 24AA32A or 24AA65.
24AA32
32K 1.8V I2CTM Smart SerialTM EEPROM
FEATURES
* Voltage operating range: 1.8V to 6.0V - Peak write current 3 mA at 6.0V - Maximum read current 150 A at 6.0V - Standby current 1 A typical * Industry standard two-wire bus protocol, I2C compatible - Including 100 kHz (1.8V) and 400 kHz (5V) modes * Self-timed ERASE and WRITE cycles * Power on/off data protection circuitry * Endurance: - 10,000,000 Erase/Write (E/W) cycles guaranteed for High Endurance Block - 1,000,000 E/W cycles guaranteed for Standard Endurance Block * 8 byte page, or byte modes available * 1 page x 8 line input cache (64 bytes) for fast write loads * Schmitt trigger, filtered inputs for noise suppression * Output slope control to eliminate ground bounce * 2 ms typical write cycle time, byte or page * Factory programming (QTP) available * Up to 8 devices may be connected to the same bus for up to 256K bits total memory * Electrostatic discharge protection > 4000V * Data retention > 200 years * 8-pin PDIP/SOIC packages * Temperature ranges - Commercial (C): 0C to +70C PDIP A0 A1 A2 VSS 1 2 3 4 24AA32 8 7 6 5 VCC NC SCL SDA
SOIC A0 A1 A2 VSS 1 2 3 4
24AA32
8 7 6 5
VCC NC SCL SDA
BLOCK DIAGRAM
A0 A1 A2 HV GENERATOR
DESCRIPTION
The Microchip Technology Inc. 24AA32 is a 4K x 8 (32K bit) Serial Electrically Erasable PROM capable of operation across a broad voltage range (1.8V to 6.0V). This device has been developed for advanced, low power applications such as personal communications or data acquisition. The 24AA32 features an input cache for fast write loads with a capacity of eight 8-byte pages, or 64 bytes. It also features a fixed 4K bit block of ultra-high endurance memory for data that changes frequently. The 24AA32 is capable of both random and sequential reads up to the 32K boundary. Functional address lines allow up to eight 24AA32 devices on the same bus, for up to 256K bits address space.
I/O CONTROL LOGIC
MEMORY CONTROL LOGIC
XDEC
EEPROM ARRAY PAGE LATCHES
I/O
SCL
CACHE
SDA VCC VSS
YDEC
SENSE AMP R/W CONTROL
Advanced CMOS technology and broad voltage range make this device ideal for low-power/low voltage, nonvolatile code PACKAGE TYPEsand data applications. The 24AA32 is available in the standard 8-pin plastic DIP and 8-pin surface mount SOIC package.
I2C is a trademark of Philips Corporation. Smart Serial is a trademark of Microchip Technology Inc.
2004 Microchip Technology Inc.
DS21124E-page 1
24AA32
1.0
1.1
ELECTRICAL CHARACTERISTICS
Maximum Ratings*
TABLE 1-1:
Name A0,A1,A2 VSS SDA SCL VCC NC
PIN FUNCTION TABLE
Function User Configurable Chip Selects Ground Serial Address/Data I/O Serial Clock +1.8V to 6.0V Power Supply No Internal Connection
VCC ..................................................................................7.0V All inputs and outputs w.r.t. VSS ............... -0.6V to VCC +1.0V Storage temperature .....................................-65C to +150C Ambient temp. with power applied ................-65C to +125C Soldering temperature of leads (10 seconds) ............. +300C ESD protection on all pins .................................................. 4 kV
*Notice: Stresses above those listed under "Maximum Ratings" may cause permanent damage to the device. This is a stress rating only and functional operation of the device at those or any other conditions above those indicated in the operational listings of this specification is not implied. Exposure to maximum rating conditions for extended periods may affect device reliability.
TABLE 1-2:
DC CHARACTERISTICS
VCC = +1.8V to 6.0V Commercial (C): Tamb Industrial (I): Tamb Parameter Symbol Min Max Units = 0C to +70C = -40C to +85C Conditions
A0, A1, A2, SCL and SDA pins: High level input voltage Low level input voltage Hysteresis of Schmitt Trigger inputs Low level output voltage Input leakage current Output leakage current Pin capacitance (all inputs/outputs) Operating current Standby current VIH VIL VHYS VOL ILI ILO CIN, COUT ICC Write ICC Read ICCS .7 VCC -- .05 VCC -- -10 -10 -- -- -- -- -- .3 Vcc -- .40 10 10 10 3 150 5 2
Note: This parameter is periodically sampled and not 100% tested.
V V V V A A pF mA A A A (Note) IOL = 3.0 mA VIN = .1V to VCC VOUT = .1V to VCC VCC = 5.0V (Note) Tamb = 25C, Fclk = 1 MHz VCC = 6.0V, SCL = 400 kHz VCC = 6.0V, SCL = 400 kHz VCC = 5.0V, SCL = SDA = VCC A0, A1, A2 = VSS (Note) VCC = 1.8V, SCL = SDA = VCC A0, A1, A2 = VSS (Note)
FIGURE 1-1:
BUS TIMING START/STOP
VHYS
SCL
TSU:STA THD:STA TSU:STO
SDA
START
STOP
DS21124E-page 2
2004 Microchip Technology Inc.
24AA32
TABLE 1-3: AC CHARACTERISTICS
VCC = 1.8V-6.0V VCC = 4.5 - 6.0V STD. MODE FAST MODE Min
Clock frequency Clock high time Clock low time SDA and SCL rise time SDA and SCL fall time START condition hold time START condition setup time Data input hold time Data input setup time STOP condition setup time Output valid from clock Bus free time FCLK THIGH TLOW TR TF THD:STA TSU:STA THD:DAT TSU:DAT TSU:STO TAA TBUF -- 4000 4700 -- -- 4000 4700 0 250 4000 -- 4700
Parameter
Symbol
Units
kHz ns ns ns ns ns ns ns ns ns ns ns
Remarks
Max
100 -- -- 1000 300 -- -- -- -- -- 3500 --
Min
-- 600 1300 -- -- 600 600 0 100 600 -- 1300
Max
400 -- -- 300 300 -- -- -- -- -- 900 --
(Note 1) (Note1) After this period the first clock pulse is generated Only relevant for repeated START condition
Output fall time from VIH min to VIL max Input filter spike suppression (SDA and SCL pins) Write cycle time Endurance High Endurance Block Rest of Array
TOF TSP TWR -- --
-- -- -- 10M 1M
250 50 5 -- --
20 +0.1 CB -- -- 10M 1M
250 50 5 -- --
ns ns
(Note 2) Time the bus must be free before a new transmission can start (Note 1), CB 100 pF (Note 3)
ms/page (Note 4) cycles 25C, Vcc = 5.0V, Block Cycle Mode (Note 5)
Note 1: Not 100% tested. CB = total capacitance of one bus line in pF. 2: As a transmitter, the device must provide an internal minimum delay time to bridge the undefined region (minimum 300 ns) of the falling edge of SCL to avoid unintended generation of START or STOP conditions. 3: The combined TSP and VHYS specifications are due to new Schmitt trigger inputs which provide improved noise and spike suppression. This eliminates the need for a Ti specification for standard operation. 4: The times shown are for a single page of 8 bytes. Multiply by the number of pages loaded into the write cache for total time. 5: This parameter is not tested but guaranteed by characterization. For endurance estimates in a specific application, please consult the Total Endurance Model which can be obtained on our website.
FIGURE 1-2:
BUS TIMING DATA
TF THIGH TLOW SCL TSU:STA THD:STA SDA IN TSP TAA SDA OUT TAA THD:DAT TSU:DAT TSU:STO
TR
TBUF
2004 Microchip Technology Inc.
DS21124E-page 3
24AA32
2.0 FUNCTIONAL DESCRIPTION
3.4 Data Valid (D)
The 24AA32 supports a bidirectional two-wire bus and data transmission protocol. A device that sends data onto the bus is defined as transmitter, and a device receiving data as receiver. The bus must be controlled by a master device which generates the serial clock (SCL), controls the bus access, and generates the START and STOP conditions, while the 24AA32 works as slave. Both master and slave can operate as transmitter or receiver but the master device determines which mode is activated. The state of the data line represents valid data when, after a START condition, the data line is stable for the duration of the HIGH period of the clock signal. The data on the line must be changed during the LOW period of the clock signal. There is one clock pulse per bit of data. Each data transfer is initiated with a START condition and terminated with a STOP condition. The number of the data bytes transferred between the START and STOP conditions is determined by the master device.
3.0
BUS CHARACTERISTICS
The following bus protocol has been defined: * Data transfer may be initiated only when the bus is not busy. * During data transfer, the data line must remain stable whenever the clock line is HIGH. Changes in the data line while the clock line is HIGH will be interpreted as a START or STOP condition. Accordingly, the following bus conditions have been defined (Figure 3-1).
3.5
Acknowledge
Each receiving device, when addressed, is obliged to generate an acknowledge signal after the reception of each byte. The master device must generate an extra clock pulse which is associated with this acknowledge bit. Note: The 24AA32 does not generate any acknowledge bits if an internal programming cycle is in progress.
3.1
Bus not Busy (A)
Both data and clock lines remain HIGH.
3.2
Start Data Transfer (B)
A HIGH to LOW transition of the SDA line while the clock (SCL) is HIGH determines a START condition. All commands must be preceded by a START condition.
A device that acknowledges must pull down the SDA line during the acknowledge clock pulse in such a way that the SDA line is stable LOW during the HIGH period of the acknowledge related clock pulse. Of course, setup and hold times must be taken into account. During reads, a master must signal an end of data to the slave by NOT generating an acknowledge bit on the last byte that has been clocked out of the slave. In this case, the slave (24AA32) will leave the data line HIGH to enable the master to generate the STOP condition.
3.3
Stop Data Transfer (C)
A LOW to HIGH transition of the SDA line while the clock (SCL) is HIGH determines a STOP condition. All operations must be ended with a STOP condition.
FIGURE 3-1:
DATA TRANSFER SEQUENCE ON THE SERIAL BUS
SCL
(A)
(B)
(D)
(D)
(C)
(A)
SDA
START CONDITION
ADDRESS OR ACKNOWLEDGE VALID
DATA ALLOWED TO CHANGE
STOP CONDITION
DS21124E-page 4
2004 Microchip Technology Inc.
24AA32
3.6 Device Addressing FIGURE 3-2:
START
A control byte is the first byte received following the start condition from the master device. The control byte consists of a four bit control code; for the 24AA32 this is set as 1010 binary for read and write operations. The next three bits of the control byte are the device select bits (A2, A1, A0). They are used by the master device to select which of the eight devices are to be accessed. These bits are in effect the three most significant bits of the word address. The last bit of the control byte defines the operation to be performed. When set to a one a read operation is selected, and when set to a zero a write operation is selected. The next two bytes received define the address of the first data byte (Figure 3-3). Because only A11...A0 are used, the upper four address bits must be zeros. The most significant bit of the most significant byte of the address is transferred first. Following the start condition, the 24AA32 monitors the SDA bus checking the device type identifier being transmitted. Upon receiving a 1010 code and appropriate device select bits, the slave device outputs an acknowledge signal on the SDA line. Depending on the state of the R/W bit, the 24AA32 will select a read or write operation.
CONTROL BYTE ALLOCATION
READ/WRITE
SLAVE ADDRESS
R/W
A
1
0
1
0
A2
A1
A0
Operation Read Write
Control Code 1010 1010
Device Select Device Address Device Address
R/W 1 0
FIGURE 3-3:
ADDRESS SEQUENCE BIT ASSIGNMENTS
ADDRESS BYTE 1
A 0 R/W A 11 A 10 A 9 A 8 A 7
CONTROL BYTE
A 2 A 1
ADDRESS BYTE 0
* * * * * * A 0
1
0
1
0
0
0
0
0
SLAVE ADDRESS
DEVICE SELECT BUS
2004 Microchip Technology Inc.
DS21124E-page 5
24AA32
4.0
4.1
WRITE OPERATION
Split Endurance
The 24AA32 acknowledges again and the master generates a stop condition. This initiates the internal write cycle, and during this time the 24AA32 will not generate acknowledge signals (Figure 4-1).
The 24AA32 is organized as a continuous 32K block of memory. However, the first 4K, starting at address 000, is rated at 10,000,000 E/W cycles guaranteed. The remainder of the array, 28K bits, is rated at 100,000 E/ W cycles guaranteed. This feature is helpful in applications in which some data change frequently, while a majority of the data change infrequently. One example would be a cellular telephone in which last-number redial and microcontroller scratch pad require a highendurance block, while speed dials and lookup tables change infrequently and so require only a standard endurance rating.
4.3
Page Write
4.2
Byte Write
Following the start condition from the master, the control code (four bits), the device select (three bits), and the R/W bit which is a logic low are clocked onto the bus by the master transmitter. This indicates to the addressed slave receiver that a byte with a word address will follow after it has generated an acknowledge bit during the ninth clock cycle. Therefore the next byte transmitted by the master is the high-order byte of the word address and will be written into the address pointer of the 24AA32. The next byte is the least significant address byte. After receiving another acknowledge signal from the 24AA32 the master device will transmit the data word to be written into the addressed memory location.
The write control byte, word address and the first data byte are transmitted to the 24AA32 in the same way as in a byte write. But instead of generating a stop condition, the master transmits up to eight pages of eight data bytes each (64 bytes total) which are temporarily stored in the on-chip page cache of the 24AA32. They will be written from cache into the EEPROM array after the master has transmitted a stop condition. After the receipt of each word, the six lower order address pointer bits are internally incremented by one. The higher order seven bits of the word address remain constant. If the master should transmit more than eight bytes prior to generating the stop condition (writing across a page boundary), the address counter (lower three bits) will roll over and the pointer will be incremented to point to the next line in the cache. This can continue to occur up to eight times or until the cache is full, at which time a stop condition should be generated by the master. If a stop condition is not received, the cache pointer will roll over to the first line (byte 0) of the cache, and any further data received will overwrite previously captured data. The stop condition can be sent at any time during the transfer. As with the byte write operation, once a stop condition is received, an internal write cycle will begin. The 64-byte cache will continue to capture data until a stop condition occurs or the operation is aborted (Figure 4-2).
FIGURE 4-1:
BYTE WRITE
S T A R T S A C K S T O P P A C K A C K A C K
BUS ACTIVITY MASTER SDA LINE BUS ACTIVITY
CONTROL BYTE
Word Address (1)
0000
Word Address (0)
DATA
FIGURE 4-2:
PAGE WRITE (FOR CACHE WRITE, SEE FIGURE 7-1)
CONTROL BYTE Word Address (1)
0000
S BUS ACTIVITY T A MASTER R T SDA LINE BUS ACTIVITY S
Word Address (2)
DATA n
DATA n + 7
S T O P P A C K
A C K
A C K
A C K
DS21124E-page 6
2004 Microchip Technology Inc.
24AA32
5.0 ACKNOWLEDGE POLLING 6.0 READ OPERATION
Since the device will not acknowledge during a write cycle, this can be used to determine when the cycle is complete (this feature can be used to maximize bus throughput). Once the stop condition for a write command has been issued from the master, the device initiates the internally timed write cycle. ACK polling can be initiated immediately. This involves the master sending a start condition followed by the control byte for a write command (R/W = 0). If the device is still busy with the write cycle, then no ACK will be returned. If the cycle is complete, then the device will return the ACK and the master can then proceed with the next read or write command. See Figure 5-1 for flow diagram. Read operations are initiated in the same way as write operations with the exception that the R/W bit of the slave address is set to one. There are three basic types of read operations: current address read, random read, and sequential read.
6.1
Current Address Read
FIGURE 5-1:
ACKNOWLEDGE POLLING FLOW
Send Write Command
The 24AA32 contains an address counter that maintains the address of the last word accessed, internally incremented by one. Therefore, if the previous access (either a read or write operation) was to address n (n is any legal address), the next current address read operation would access data from address n + 1. Upon receipt of the slave address with R/W bit set to one, the 24AA32 issues an acknowledge and transmits the eight bit data word. The master will not acknowledge the transfer but does generate a stop condition and the 24AA32 discontinues transmission (Figure 6-1).
6.2
Send Stop Condition to Initiate Write Cycle
Random Read
Send Start
Send Control Byte with R/W = 0
Did Device Acknowledge (ACK = 0)? Yes Next Operation
No
Random read operations allow the master to access any memory location in a random manner. To perform this type of read operation, first the word address must be set. This is done by sending the word address to the 24AA32 as part of a write operation (R/W bit set to 0). After the word address is sent, the master generates a start condition following the acknowledge. This terminates the write operation, but not before the internal address pointer is set. Then the master issues the control byte again but with the R/W bit set to a one. The 24AA32 will then issue an acknowledge and transmit the eight bit data word. The master will not acknowledge the transfer but does generate a stop condition which causes the 24AA32 to discontinue transmission (Figure 6-2).
FIGURE 6-1:
CURRENT ADDRESS READ
BUS ACTIVITY MASTER S T A R T S A C K N O A C K S T O P P
CONTROL BYTE
DATA BYTE
SDA LINE
BUS ACTIVITY
2004 Microchip Technology Inc.
DS21124E-page 7
24AA32
6.3 Contiguous Addressing Across Multiple Devices
To provide sequential reads the 24AA32 contains an internal address pointer which is incremented by one at the completion of each operation. This address pointer allows the entire memory contents to be serially read during one operation. The address pointer, however, will not roll over from address 07FF to address 0000. It will roll from 07FF to unused memory space.
The device select bits A2, A1, A0 can be used to expand the contiguous address space for up to 256K bits by adding up to eight 24AA32's on the same bus. In this case, software can use A0 of the control byte as address bit A12, A1 as address bit A13, and A2 as address bit A14.
6.5
Noise Protection
6.4
Sequential Read
Sequential reads are initiated in the same way as a random read except that after the 24AA32 transmits the first data byte, the master issues an acknowledge as opposed to the stop condition used in a random read. This acknowledge directs the 24AA32 to transmit the next sequentially addressed 8 bit word (Figure 6-3). Following the final byte transmitted to the master, the master will NOT generate an acknowledge but will generate a stop condition.
The SCL and SDA inputs have filter circuits which suppress noise spikes to ensure proper device operation even on a noisy bus. All I/O lines incorporate Schmitt triggers for 400 kHz (Fast Mode) compatibility.
FIGURE 6-2:
S T A R T SDA LINE
RANDOM READ
S T A R T
CONTROL BYTE
WORD ADDRESS (1)
WORD ADDRESS (0)
CONTROL BYTE
DATA n
S T O P
S
A C K
0000 A C K A C K
S
A C K N O A C K
P
BUS ACTIVITY:
FIGURE 6-3:
SEQUENTIAL READ
BUS ACTIVITY MASTER SDA LINE BUS ACTIVITY
CONTROL BYTE
DATA n
DATA n + 1
DATA n + 2
DATA n + x
S T O P P N O A C K
A C K
A C K
A C K
A C K
DS21124E-page 8
2004 Microchip Technology Inc.
24AA32
6.6 PAGE CACHE AND ARRAY MAPPING
The cache is a 64 byte (8 pages x 8 bytes) FIFO buffer. The cache allows the loading of up to 64 bytes of data before the write cycle is actually begun, effectively providing a 64-byte burst write at the maximum bus rate. Whenever a write command is initiated, the cache starts loading and will continue to load until a stop bit is received to start the internal write cycle. The total length of the write cycle will depend on how many pages are loaded into the cache before the stop bit is given. Maximum cycle time for each page is 5 ms. Even if a page is only partially loaded, it will still require the same cycle time as a full page. If more than 64 bytes of data are loaded before the stop bit is given, the address pointer will 'wrap around' to the beginning of cache page 0 and existing bytes in the cache will be overwritten. The device will not respond to any commands while the write cycle is in progress. page 0 (of the cache). When the stop bit is sent, page 0 of the cache is written to page 3 of the array. The remaining pages in the cache are then loaded sequentially to the array. A write cycle is executed after each page is written. If a partially loaded page in the cache remains when the STOP bit is sent, only the bytes that have been loaded will be written to the array.
6.9
Power Management
6.7
Cache Write Starting at a Page Boundary
This design incorporates a power standby mode when the device is not in use and automatically powers off after the normal termination of any operation when a stop bit is received and all internal functions are complete. This includes any error conditions, ie. not receiving an acknowledge or stop condition per the two-wire bus specification. The device also incorporates VDD monitor circuitry to prevent inadvertent writes (data corruption) during low-voltage conditions. The VDD monitor circuitry is powered off when the device is in standby mode in order to further reduce power consumption.
7.0
7.1
PIN DESCRIPTIONS
A0, A1, A2 Chip Address Inputs
If a write command begins at a page boundary (address bits A2, A1 and A0 are zero), then all data loaded into the cache will be written to the array in sequential addresses. This includes writing across a 4K block boundary. In the example shown below, (Figure 4-2) a write command is initiated starting at byte 0 of page 3 with a fully loaded cache (64 bytes). The first byte in the cache is written to byte 0 of page 3 (of the array), with the remaining pages in the cache written to sequential pages in the array. A write cycle is executed after each page is written. Since the write begins at page 3 and 8 pages are loaded into the cache, the last 3 pages of the cache are written to the next row in the array.
The A0..A2 inputs are used by the 24AA32 for multiple device operation and conform to the two-wire bus standard. The levels applied to these pins define the address block occupied by the device in the address map. A particular device is selected by transmitting the corresponding bits (A2, A1, A0) in the control byte (Figure 3-3).
7.2
SDA Serial Address/Data Input/Output
6.8
Cache Write Starting at a Non-Page Boundary
This is a bidirectional pin used to transfer addresses and data into and data out of the device. It is an open drain terminal, therefore the SDA bus requires a pullup resistor to VCC (typical 10K for 100 kHz, 2 K for 400 kHz) For normal data transfer SDA is allowed to change only during SCL low. Changes during SCL high are reserved for indicating the START and STOP conditions.
When a write command is initiated that does not begin at a page boundary (i.e., address bits A2, A1 and A0 are not all zero), it is important to note how the data is loaded into the cache, and how the data in the cache is written to the array. When a write command begins, the first byte loaded into the cache is always loaded into page 0. The byte within page 0 of the cache where the load begins is determined by the three least significant address bits (A2, A1, A0) that were sent as part of the write command. If the write command does not start at byte 0 of a page and the cache is fully loaded, then the last byte(s) loaded into the cache will roll around to page 0 of the cache and fill the remaining empty bytes. If more than 64 bytes of data are loaded into the cache, data already loaded will be overwritten. In the example shown in Figure 7-2, a write command has been initiated starting at byte 2 of page 3 in the array with a fully loaded cache of 64 bytes. Since the cache started loading at byte 2, the last two bytes loaded into the cache will'roll over' and be loaded into the first two bytes of
7.3
SCL Serial Clock
This input is used to synchronize the data transfer from and to the device.
2004 Microchip Technology Inc.
DS21124E-page 9
24AA32
FIGURE 7-1: CACHE WRITE TO THE ARRAY STARTING AT A PAGE BOUNDARY
1 Write command initiated at byte 0 of page 3 in the array; First data byte is loaded into the cache byte 0. cache page 0 cache byte 0 cache byte 1 *** cache byte 7 cache page 1 cache page 2 bytes 8-15 bytes 16-23 *** cache page 7 bytes 56-63
2 64 bytes of data are loaded into cache.
3 Write from cache into array initiated by STOP bit. Page 0 of cache written to page 3 of array. Write cycle is executed after every page is written. page 0 page 1 page 2 page 0 page 1 page 2 byte 0 byte 1 ***
4 Remaining pages in cache are written to sequential pages in array. byte 7 page 4 page 4 *** *** page 7 array row n page 7 array row n + 1
page 3
5 Last page in cache written to page 2 in next row.
FIGURE 7-2:
CACHE WRITE TO THE ARRAY STARTING AT A NON-PAGE BOUNDARY
1 Write command initiated; 64 bytes of data loaded into cache starting at byte 2 of page 0. cache byte 1 cache byte 2 cache byte 7 2 Last 2 bytes loaded 'roll over' to beginning. cache page 7 bytes 56-63
Last 2 bytes loaded into page 0 of cache.
3 cache byte 0
***
cache page 1 cache page 2 bytes 8-15 bytes 16-23
***
4 Write from cache into array initiated by STOP bit. 5 Remaining bytes in cache are Page 0 of cache written to page 3 of array. Write cycle is executed after every page is written. written sequentially to array. page 7 array row n page 7 array row n+1
page 0 page 1 page 2 page 0 page 1 page 2
byte 0
byte 1
byte 2
byte 3 page 3
byte 4
***
byte 7
page 4 page 4
*** ***
6 Last 3 pages in cache written to next row in array.
DS21124E-page 10
2004 Microchip Technology Inc.
24AA32
24AA32 Product Identification System
To order or to obtain information, e.g., on pricing or delivery, please use the listed part numbers, and refer to the factory or the listed sales offices.
24AA32 -
/P Package: Temperature Range: Device: P = Plastic DIP (300 mil Body), 8-lead SM = Plastic SOIC (207 mil Body), 8-lead Blank = 0C to +70C 24AA32 24AA32T 16K I2C Serial EEPROM 16K I2C Serial EEPROM (Tape and Reel)
Sales and Support
Data Sheets Products supported by a preliminary Data Sheet may have an errata sheet describing minor operational differences and recommended workarounds. To determine if an errata sheet exists for a particular device, please contact one of the following: 1. Your local Microchip sales office 2. The Microchip Corporate Literature Center U.S. FAX: (602) 786-7277 3. The Microchip Worldwide Web Site (www.microchip.com)
2004 Microchip Technology Inc.
DS21124E-page 11
24AA32
NOTES:
DS21124E-page 12
2004 Microchip Technology Inc.
Note the following details of the code protection feature on Microchip devices: * * Microchip products meet the specification contained in their particular Microchip Data Sheet. Microchip believes that its family of products is one of the most secure families of its kind on the market today, when used in the intended manner and under normal conditions. There are dishonest and possibly illegal methods used to breach the code protection feature. All of these methods, to our knowledge, require using the Microchip products in a manner outside the operating specifications contained in Microchip's Data Sheets. Most likely, the person doing so is engaged in theft of intellectual property. Microchip is willing to work with the customer who is concerned about the integrity of their code. Neither Microchip nor any other semiconductor manufacturer can guarantee the security of their code. Code protection does not mean that we are guaranteeing the product as "unbreakable."
*
* *
Code protection is constantly evolving. We at Microchip are committed to continuously improving the code protection features of our products. Attempts to break Microchip's code protection feature may be a violation of the Digital Millennium Copyright Act. If such acts allow unauthorized access to your software or other copyrighted work, you may have a right to sue for relief under that Act.
Information contained in this publication regarding device applications and the like is intended through suggestion only and may be superseded by updates. It is your responsibility to ensure that your application meets with your specifications. No representation or warranty is given and no liability is assumed by Microchip Technology Incorporated with respect to the accuracy or use of such information, or infringement of patents or other intellectual property rights arising from such use or otherwise. Use of Microchip's products as critical components in life support systems is not authorized except with express written approval by Microchip. No licenses are conveyed, implicitly or otherwise, under any intellectual property rights.
Trademarks The Microchip name and logo, the Microchip logo, Accuron, dsPIC, KEELOQ, microID, MPLAB, PIC, PICmicro, PICSTART, PRO MATE, PowerSmart, rfPIC, and SmartShunt are registered trademarks of Microchip Technology Incorporated in the U.S.A. and other countries. AmpLab, FilterLab, MXDEV, MXLAB, PICMASTER, SEEVAL, SmartSensor and The Embedded Control Solutions Company are registered trademarks of Microchip Technology Incorporated in the U.S.A. Analog-for-the-Digital Age, Application Maestro, dsPICDEM, dsPICDEM.net, dsPICworks, ECAN, ECONOMONITOR, FanSense, FlexROM, fuzzyLAB, In-Circuit Serial Programming, ICSP, ICEPIC, Migratable Memory, MPASM, MPLIB, MPLINK, MPSIM, PICkit, PICDEM, PICDEM.net, PICLAB, PICtail, PowerCal, PowerInfo, PowerMate, PowerTool, rfLAB, rfPICDEM, Select Mode, Smart Serial, SmartTel and Total Endurance are trademarks of Microchip Technology Incorporated in the U.S.A. and other countries. SQTP is a service mark of Microchip Technology Incorporated in the U.S.A. All other trademarks mentioned herein are property of their respective companies. (c) 2004, Microchip Technology Incorporated, Printed in the U.S.A., All Rights Reserved. Printed on recycled paper.
Microchip received ISO/TS-16949:2002 quality system certification for its worldwide headquarters, design and wafer fabrication facilities in Chandler and Tempe, Arizona and Mountain View, California in October 2003. The Company's quality system processes and procedures are for its PICmicro(R) 8-bit MCUs, KEELOQ(R) code hopping devices, Serial EEPROMs, microperipherals, nonvolatile memory and analog products. In addition, Microchip's quality system for the design and manufacture of development systems is ISO 9001:2000 certified.
2004 Microchip Technology Inc.
DS21124E-page 13
WORLDWIDE SALES AND SERVICE
AMERICAS
Corporate Office
2355 West Chandler Blvd. Chandler, AZ 85224-6199 Tel: 480-792-7200 Fax: 480-792-7277 Technical Support: 480-792-7627 Web Address: www.microchip.com
China - Beijing
Unit 706B Wan Tai Bei Hai Bldg. No. 6 Chaoyangmen Bei Str. Beijing, 100027, China Tel: 86-10-85282100 Fax: 86-10-85282104
Singapore
200 Middle Road #07-02 Prime Centre Singapore, 188980 Tel: 65-6334-8870 Fax: 65-6334-8850
Taiwan
Kaohsiung Branch 30F - 1 No. 8 Min Chuan 2nd Road Kaohsiung 806, Taiwan Tel: 886-7-536-4816 Fax: 886-7-536-4817
China - Chengdu
Rm. 2401-2402, 24th Floor, Ming Xing Financial Tower No. 88 TIDU Street Chengdu 610016, China Tel: 86-28-86766200 Fax: 86-28-86766599
Atlanta
3780 Mansell Road, Suite 130 Alpharetta, GA 30022 Tel: 770-640-0034 Fax: 770-640-0307
Taiwan
Taiwan Branch 11F-3, No. 207 Tung Hua North Road Taipei, 105, Taiwan Tel: 886-2-2717-7175 Fax: 886-2-2545-0139
Boston
2 Lan Drive, Suite 120 Westford, MA 01886 Tel: 978-692-3848 Fax: 978-692-3821
China - Fuzhou
Unit 28F, World Trade Plaza No. 71 Wusi Road Fuzhou 350001, China Tel: 86-591-7503506 Fax: 86-591-7503521
Taiwan
Taiwan Branch 13F-3, No. 295, Sec. 2, Kung Fu Road Hsinchu City 300, Taiwan Tel: 886-3-572-9526 Fax: 886-3-572-6459
Chicago
333 Pierce Road, Suite 180 Itasca, IL 60143 Tel: 630-285-0071 Fax: 630-285-0075
China - Hong Kong SAR
Unit 901-6, Tower 2, Metroplaza 223 Hing Fong Road Kwai Fong, N.T., Hong Kong Tel: 852-2401-1200 Fax: 852-2401-3431
Dallas
16200 Addison Road, Suite 255 Addison Plaza Addison, TX 75001 Tel: 972-818-7423 Fax: 972-818-2924
EUROPE
Austria
Durisolstrasse 2 A-4600 Wels Austria Tel: 43-7242-2244-399 Fax: 43-7242-2244-393
China - Shanghai
Room 701, Bldg. B Far East International Plaza No. 317 Xian Xia Road Shanghai, 200051 Tel: 86-21-6275-5700 Fax: 86-21-6275-5060
Detroit
Tri-Atria Office Building 32255 Northwestern Highway, Suite 190 Farmington Hills, MI 48334 Tel: 248-538-2250 Fax: 248-538-2260
Denmark
Regus Business Centre Lautrup hoj 1-3 Ballerup DK-2750 Denmark Tel: 45-4420-9895 Fax: 45-4420-9910
China - Shenzhen
Rm. 1812, 18/F, Building A, United Plaza No. 5022 Binhe Road, Futian District Shenzhen 518033, China Tel: 86-755-82901380 Fax: 86-755-8295-1393
Kokomo
2767 S. Albright Road Kokomo, IN 46902 Tel: 765-864-8360 Fax: 765-864-8387
France
Parc d'Activite du Moulin de Massy 43 Rue du Saule Trapu Batiment A - ler Etage 91300 Massy, France Tel: 33-1-69-53-63-20 Fax: 33-1-69-30-90-79
China - Shunde
Room 401, Hongjian Building, No. 2 Fengxiangnan Road, Ronggui Town, Shunde District, Foshan City, Guangdong 528303, China Tel: 86-757-28395507 Fax: 86-757-28395571
Los Angeles
25950 Acero St., Suite 200 Mission Viejo, CA 92691 Tel: 949-462-9523 Fax: 949-462-9608
China - Qingdao
Rm. B505A, Fullhope Plaza, No. 12 Hong Kong Central Rd. Qingdao 266071, China Tel: 86-532-5027355 Fax: 86-532-5027205
Germany
Steinheilstrasse 10 D-85737 Ismaning, Germany Tel: 49-89-627-144-0 Fax: 49-89-627-144-44
San Jose
1300 Terra Bella Avenue Mountain View, CA 94043 Tel: 650-215-1444 Fax: 650-961-0286
India
Divyasree Chambers 1 Floor, Wing A (A3/A4) No. 11, O'Shaugnessey Road Bangalore, 560 025, India Tel: 91-80-22290061 Fax: 91-80-22290062
Italy
Via Salvatore Quasimodo, 12 20025 Legnano (MI) Milan, Italy Tel: 39-0331-742611 Fax: 39-0331-466781
Toronto
6285 Northam Drive, Suite 108 Mississauga, Ontario L4V 1X5, Canada Tel: 905-673-0699 Fax: 905-673-6509
Japan
Yusen Shin Yokohama Building 10F 3-17-2, Shin Yokohama, Kohoku-ku, Yokohama, Kanagawa, 222-0033, Japan Tel: 81-45-471- 6166 Fax: 81-45-471-6122
Netherlands
Waegenburghtplein 4 NL-5152 JR, Drunen, Netherlands Tel: 31-416-690399 Fax: 31-416-690340
ASIA/PACIFIC
Australia
Microchip Technology Australia Pty Ltd Unit 32 41 Rawson Street Epping 2121, NSW Sydney, Australia Tel: 61-2-9868-6733 Fax: 61-2-9868-6755
Korea
168-1, Youngbo Bldg. 3 Floor Samsung-Dong, Kangnam-Ku Seoul, Korea 135-882 Tel: 82-2-554-7200 Fax: 82-2-558-5932 or 82-2-558-5934
United Kingdom
505 Eskdale Road Winnersh Triangle Wokingham Berkshire, England RG41 5TU Tel: 44-118-921-5869 Fax: 44-118-921-5820
07/12/04
2004 Microchip Technology Inc.

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